1. Field of the Invention
The invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device.
2. Discussion of the Related Art
In general, among flat panel display (FPD) devices, liquid crystal display (LCD) devices have been in the spotlight as the next generation display devices for cellular phones, personal computer monitors or televisions because of their superior visibility, low power consumption and low generation of heat.
Liquid crystal display (LCD) devices use the optical anisotropy and polarization properties of liquid crystal molecules of a liquid crystal layer to produce an image. The liquid crystal molecules have long, thin shapes, and the liquid crystal molecules can be arranged along a certain direction. The alignment direction of the liquid crystal molecules can be controlled by varying the intensity of an electric field applied to the liquid crystal layer. Accordingly, the alignment of the liquid crystal molecules are changed by the electric field. Light is transmitted and refracted according to the alignment of the liquid crystal molecules to display an image.
A related art liquid crystal display device will be explained with reference to the accompanying drawings.
FIG. 1 is a plan view, schematically illustrating an array substrate for a liquid crystal display (LCD) device according to the related art.
In FIG. 1, an array substrate of a related art LCD device includes a display area AA and a non-display area NAA. Images are displayed in the display area AA.
First to mth gate lines GL1 to GLm and first to nth data lines DL1 to DLn are formed in the display area AA on a substrate 10 and are arranged in a matrix form. The first to mth gate lines GL1 to GLm and the first to nth data lines DL1 to DLn cross each other to define pixel regions P. The first to mth gate lines GL1 to GLm receive scanning signals, and the first to nth data lines DL1 to DLn receive data signals.
A thin film transistor T is formed at each crossing point of the first to mth gate lines GL1 to GLm and the first to nth data lines DL1 to DLn. A pixel electrode 80 is formed in each pixel region P and is connected to the thin film transistor T.
The first to mth gate lines GL1 to GLm are electrically connected with first to mth gate pads GP1 to GPm through first to mth gate link lines GLL1 to GLLm, respectively. The first to nth data lines DL1 to DLn are electrically connected with first to nth data pads DP1 to DPn through first to nth data link lines DLL1 to DLLn, respectively.
The first to mth gate pads GP1 to GPm are partially exposed by first to mth gate pad contact holes (not shown) and are connected to first to mth gate pad terminals (not shown), which are formed on the same layer and of the same material as the pixel electrodes 80, through the first to mth gate pad contact holes (not shown), respectively. The first to nth data pads DP1 to DPn are partially exposed by first to nth data pad contact holes (not shown) and are connected to first to nth data pad terminals (not shown), which are formed on the same layer and of the same material as the pixel electrodes 80, through the first to nth data pad contact holes (not shown), respectively.
The first to mth gate pad terminals (not shown) and the first to nth data pad terminals (not shown) are connected to gate and data driving integrated circuits (ICs) (not shown), which are attached at respective sides of the substrate 10 by a tape automated bonding (TAB) packaging process. The first to mth gate pad terminals supply the first to mth gate lines GL1 to GLm with the scanning signals from the gate driving integrated circuit. The first to nth data pad terminals provide the first to nth data lines DL1 to DLn with the data signals from the data driving integrated circuit.
FIG. 2 is an enlarged view of a region A of FIG. 1, and FIG. 3 is an enlarged view of a left half part of the region A of FIG. 2. FIG. 2 and FIG. 3 illustrate the non-display area NAA on the substrate 10 including the display area AA of FIG. 1 and the non-display area NAA, and in particular, a data pad area PA.
In FIG. 2 and FIG. 3, the first to nth data pads DP1 to DPn are formed in the data pad area PA. The first to nth data pads DP1 to DPn are spaced apart from each other with a pad pitch P1 therebetween. The first to nth data link lines DLL1 to DLLn are connected to the first to nth data pads DP1 to DPn, respectively. The first to nth data link lines DLL1 to DLLn provide signals to the first to nth data lines DL1 to DLn of FIG. 1.
The first to nth data link lines DLL1 to DLLn include vertical portions, which are connected to the first to nth data pads DP1 to DPn, and inclined portions, which aslant and extend from the vertical portions. The first to nth data link lines DLL1 to DLLn have the same width W, and link pitches P2 between adjacent data link lines including the width of one of the adjacent data link lines are designed at regular intervals regardless of the vertical portions and the inclined portions. Accordingly, link spaces F2 between facing side surfaces of adjacent data link lines are the differences between the link pitches P2 and the widths W.
In the above-mentioned structure, the lengths of the data link lines become longer toward the first data link line DLL1 from the (n/2−1)th data link line DLL(n/2−1) and toward the nth data link line DLLn from the (n/2+1)th data link line DLL(n/2+1) based on the (n/2)th data link line DLL(n/2).
Generally, electrical resistance is proportional to a length and reciprocal proportional to a cross sectional area. That is, as a signal line gets longer, the electrical resistance of the signal line becomes higher because electrons pass through a longer path. Since the first to nth data link lines DLL1 to DLLn have the same width W, the resistances of the data link lines get higher as the data link lines become farther from the (n/2)th data link line and go to left and right peripheral regions.
Recently, research has been conducted to decrease the number of driver ICs and reduce manufacturing costs. However, as the size of LC panels increases, the number of the data link lines increases, and the lengths of the data link lines in the left and right peripheral regions become much longer.
Moreover, in LCD devices having high resolution, while the data link lines increase, the link pitches between adjacent data link lines decrease. This causes the data link lines in the left and right peripheral regions have much higher electrical resistance than the data link lines in the central region between the left and right peripheral regions, and there occur uncharged problems.